Until 2019, the world was called VUCA (Volatility, Uncertainty, Complexity, Ambiguity) world, and it was a terrible situation. Still, the semiconductor market was thriving thanks to ICAC5 (IoT, Cloud, AI, Car, 5G), which I think is because semiconductor technology has accurately shown the future. COVID-19 struck the world at the end of 2019, and the world became worse than before, just like hell. However the semiconductor markets. This is thanks to DX (Digital Transformation) and GX (Green Transformation) in addition to ICAC5. Semiconductor is surely the key technology for both of DX and GX. The world after COVID-19 will also proceed with ICAC5 + GX + DX, all thanks to the progress of semiconductors, the revolution, and the innovations that cause them. In this talk, I would like to explain about how ICAC5, DX, and GX will drive the semiconductor market, semiconductor technology will revolutionize, and manufacturing equipment should support. My story is from the perspective of the equipment manufacturer. We would appreciate your guidance from set makers and device makers.

Dr. Manabu Tsujimura is at present Fellow of EBARA CORPORATION, who has worked at EBARA CORPORATION since 1974, CTO of EBARA CORPORATION since 2009, President of Precision Machinery Company from 2011 to 2015, He received a Dr. degree in Engineering field from Tokyo Metropolitan University, Tokyo, Japan. He is Fellow of JSME (The Japan Society of Mechanical Engineerings). He has contributed to academies and associations as; Visiting Professor of Clarkson University, Visiting Professor of Hanyang University, Visiting Professor of SKKU, Visiting Professor of NTUST, Visiting Professor of Fudan University, Vice chair of SEAJ (Chair in 2017 and 2018), Vice chair of JVIA (Chair in 2012 and 2013). He has more than 100 patent applications, and has written more than 100 papers.

Due to advent of the internet of things (IoT), the prevalence of social networking services (SNSs), and production of photos and videos at ever-higher resolution, the volume of data generated worldwide is growing exponentially. In the field of information processing, real-time performance is considered an important requirement as a huge amount of data must be managed by big-data systems or indefinitely stored by data centers and cloud service systems. In this situation, high-capacity storage is required to process, store and manage large quantities of data at high speed and low power consumption. Furthermore, for smartphone, tablet, memory card and other power-sensitive applications, demand for storage with lower power consumption is increasing. The vertically stacked three-dimensional (3D) flash memory will be the solution satisfying the market requirement. In this paper, the concept, technologies and metallization challenges for 3D flash memory will be presented.

Masayoshi Tagami received the B.E. and M.E. degrees from Tokyo Institute of Technology in 1996 and 1998, respectively, and received the Ph.D. in electrical engineering from Tohoku University in 2015. He joined NEC Corporation in 1998, and had engaged in research and development of BEOL process integration for logic LSIs. He joined Toshiba Corporation (current Kioxia Corporation) in 2013, and has engaged in research and development of BEOL process integration for 3D flash memory.

STT-MRAM is the only scalable emebedded non-volatile memory (eNVM) that is capable of high density, high speed, high endurance. These unique attributes differentiate STT-MRAM from other emerging eNVM technologies such as ReRAM. However, as embedded Flash (eFlash) is not expected to scale down beyond 28 nm, major foundries have been developing STT-MRAM to replace eFlash rather than fully exploiting the unique attributes of STT-MRAM. In this paper, we review the current status of STT-MRAM products and explore emerging STT-MRAM applications beyond eFlash replacement. We also discuss scalability challenges for STT-MRAM at the advanced nodes.

Kangho Lee is a semiconductor technologist who specializes in embedded NVM technology, particularly STT-MRAM. He is the Master of Samsung Electronics, currently leading an MRAM team at Samsung Foundry. Before joining Samsung Electronics, he had worked on STT-MRAM technology at Qualcomm and GlobalFoundries, contributing to MRAM technology advances and delivering the world-first STT-MRAM products. He received his B.S. in Electrical Engineering from Seoul National University in 2000 and his Ph.D. in Electrical Engineering from Purdue University in 2007. He is the senior member of IEEE and holds > 50 U.S.

Nowadays, the Internet-Of-Things (IoT) consists of a variety of LSIs. To use in different situations, small, multi-functional and high-performance LSIs have been strongly needed. In the field of CMOS Image Sensor (CIS), there has been high demand for new functions that can respond to various photo-taking scenes. We have developed a stacked Back-Illuminated-CIS (BI-CIS), composed of conventional BI-CIS technology and standard logic technology. The stacked BI-CIS layers back-illuminated structure pixels onto chips containing the circuit section for signal processing. The newly attached logic circuits have achieved the advanced features such as higher sensitivity and high dynamic range (HDR) movie. In the early types of stacked BI-CIS the through-silicon-via (TSV) technology was used to electrically connect CIS chip and logic circuits. To improve the manufacturing productivity, we have recently introduced the wafer-level Cu-Cu hybrid bonding technology in place of TSV technology. The Cu-Cu hybrid bonding technology provides us further merits such as fine-pitch and large-scale connection and hence additional new functions.

Yoshihisa Kagawa is a Senior Manager of the Research Division in Sony Semiconductor Solutions Corporation. He received his M.S. degrees from Kyoto University, Japan. He joined Sony Corporation and has nearly 20 years of experience in process integration. In recent years, he has been managing process integration for the 3D stacked CMOS image sensor. Sony Semiconductor Solutions Corporation was awarded the 65th (2018) Okochi Memorial Technology Prize from the Okochi Memorial Foundation for Cu-Cu direct bonding technology and he played a key role in this.

An evolution of Artificial Intelligence (AI) expands from could to edge, and training to inference, in which the neural network inference needs high speed, energy efficiency and flexibility to support various applications in the edge. Namely. Artificial Intelligence/Internet of Things (AIoT) is realized by the combination of smarter AI technologies with more efficient Internet of things (IoT) hardware. To satisfying the requirements, beyond von Neumann (e.g. new computing-in-memory (CIM) architecture) approach is recognized as one of the strong candidates. Thus, not only CMOS scaling, but also emerging memoires and switches integrated in Cu-BEOL are of great interest and becoming research topics to realize the AIoT systems.
NanoBridge (NB) (a.k.a. Atom switch) is categorized in a cation type resistive-change device, in which the resistance of NBs can be changed by applying a voltage and Cu bridge is formed in the electrolyte, which are called atomic switch, solid-electrolyte switch, programmable metallization cell (PMC), conducting bridge or CBRAM. We propose a field programmable gate array using NBs (NBFPGA) for the next possible solution of the inference accelerator, having nonvolatility, better speed and lower power. Also, NB itself has high radiation-tolerance, expanding the opportunities for space rad-hard application.
This talk provides a review for development of NBs in the last decade and introduce key process technologies of NBs inspired by Cu-BEOL developments. A future potential of NBs for AIoT application will be discussed.

Munehiro Tada is a VP Engineering at NanoBridge Semiconductor, Inc. (NBS). He is responsible for technology and product developments, including identifying disruptive technologies, monitoring the global technology landscape and coordinating research outside of NBS. He joined NEC Corporation in 1999, where he was engaged in developments of FEOL, BEOL and NVM. From 2007 to 2008, he was a visiting scholar at Stanford University, Stanford, CA. His research interests include emerging technologies, interconnects, memory, and design-technology co-optimization. He has published over 130 peer-reviewed technical papers, on a wide range of topics of interconnect scaling and nonvolatile memory, including 16-iedm, 15-vlsi, 8-iitc, 2-isscc and 17-ted papers. He holds a Ph.D. and is an IEEE Fellow.

Scaling of Cu interconnect dimensions is becoming increasingly difficult due to the increase in the resistance-capacitance (RC) delay which will cause a degradation in the chip performance. The increase in Cu line resistance with decreasing area may be the limiting factor of the overall circuit performance. Nowadays there are two proposals to mitigate this increase:1) increase the Cu area by scaling down the barrier and liner and 2) replace Cu for other materials (i.e. Co, Ru…). In both proposals, reliability is a key metric that needs to be assessed. During this workshop we will first address the impact of Cu scaling on different reliability aspects (TDDB, Electromigration and Stress Induced Voiding). Next, we will show the benefit of via prefill schemes and to end, the excellent reliability performance for scaled interconnects metallized with alternative metals will be discussed, where we identify the main challenge will be the self-heating dissipation.

Olalla Varela Pedreira received the M.Sc. degree in telecommunication engineering from the University of Vigo, Vigo, Spain. In 2007, she joined imec as a Research Engineer, where she worked on the optical characterization of microelectromechanical system (MEMS) devices in the Microsystems Reliability team. Her activities expanded from 2012 towards the field of 3D technologies, for which she was driving activities in optical profilometry as well as involved in electrical characterization of 3D stacks and TSV interconnects.

The saturation of silicon technology scaling in combination with the rising challenge of extracting information from large amounts of unstructured data, demands new computing architectures and hardware integration schemes to be developed. I will report on our progress in co-integrating new materials on silicon for high bandwidth optical communication in support of established computing systems. Furthermore, analog signal processing will be introduced to overcome some of the performance and efficiency bottlenecks observed in today’s Von Neumann architectures, going to in-memory computing. Electrical and photonic technological approaches for implementing efficient accelerators for neuromorphic computing will be discussed as well as their prospects and challenges.

Bert Offrein received his Ph.D. degree in nonlinear integrated optics from the University of Twente (NL) in 1994. He then joined IBM Research – Zurich and contributed to establishing and commercializing adaptive integrated optical technology for DWDM networks. From 2004 to 2016, Bert Offrein was managing the photonics group, addressing optical interconnects for computing systems. Since 2016, he is leading the neuromorphic devices and systems group, focussing on novel hardware for neural networks. Bert Offrein is a principal research staff member at IBM Research and the co-author of over 150 publications and the co-inventor of more than 35 patents.