Advanced interconnect challenges beyond 5nm and possible solutions
Kichul Park
Samsung Electronics, South Korea
Abstract
As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance (IR drop in power distribution network and RC delay in signal lines), power (capacitance of signal lines), area (yield loss due to scaling), and cost (increase in the number of EUV lithography layers). Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as new liner that can enable more aggressive thickness scaling. For capacitance reduction, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss due to scaling mainly comes from Cu void or bridge defects. Cu filling friendly damascene profile is being introduced, and heavy OPC optimizations based on layout studies can help to increase margin for the bridge defects. Since increasing BEOL cost is a critical challenge, single EUV patterning replacing double patterning is being actively investigated. In parallel to the conventional scaling, disruptive structural changes such as backside power distribution network, and innovative materials such as 2D conductors are also being researched, and will be discussed.
CV
KC Park received the Ph.D. degree in metallurgical engineering from Seoul National University, Korea, in 1998. Since 1998, he has been with Samsung Electronics. He participated in IBM Alliance program for 65nm logic technology development as a BEOL process integrator from 2004 to 2006. He has developed Samsung Foundry’s logic BEOL interconnect at 45nm, 28nm, 14nm, and 10nm nodes. Now he is in charge of beyond 5nm BEOL interconnect development.
Opportunities and challenges brought by 3D-sequential integration
Perrine Batude
Senior scientist and project manager, CEA-Leti, France
Abstract
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors, namely i) pursuing Moore’s law without resorting to MOSFETs scaling, ii) enabling alternative computing paradigms through close proximity between logic and memory units, iii) offering new heterogeneous co‐integrations schemes for smart sensor arrays and iv) adding low cost functionalities above ICs. This presentation will give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.
CV
Perrine Batude is a senior scientist and project manager at CEA-Leti, Grenoble, France. She received the M.S degree in physics and engineering from Grenoble INP. During her Ph.D. obtained in 2009, she began the early development of 3D sequential integration in Leti. She joined CEA-Leti in 2009 as a device engineer in the Electronics Nanodevices Laboratory. In the frame of these activities, she received four Best Student Paper Awards : at INFOS 2007 in Athens , at ICICDT 2008 in Grenoble, at ECS Fall Meeting 2008 in Honolulu and at IEDM 2009 in Baltimore. She is author or co-author of more than 80 papers published in conferences and journals. Her ten years’ experience in 3D sequential integration is internationally recognized, she has been invited in more than 10 conferences including IEDM and VLSI to present CEA-Leti’s work on the subject. She served in the ‘Process technology’ sub-committee of the International Electron Device Meeting (IEDM).
EUV patterning considerations for BEOL scaling
Nilson Felix
Director, Process Technology, IBM Research, USA
Abstract
In 2015, IBM announced the first 7 nm test chip patterned with Extreme Ultraviolet Lithography (EUV) technology, enabling 36nm back end of the line (BEOL) metal pitch. Five years later, this technology became the mainstream enabler for 7 nm node manufacturing, including the recent announcement of IBM’s Power10 high-performance chip. In this talk, we will review some of the challenges and patterning solutions that allow successful implementation of high-performance design definitions. We will also discuss our current efforts to extend the use of single expose EUV to 28nm pitch, as well as look forward to the patterning challenges yet to be solved for BEOL scaling beyond the 2nm node. In all cases, process improvements and co-optimization are viewed in the context of their impact to electrical yield and device performance.
CV
Nelson Felix joined IBM in 2008 and is currently the Director of Process Technology at IBM Research in Albany, NY. In this role, Nelson is responsible for the demonstration and enablement of new tooling, processes, materials, and metrology to support IBM’s leading-edge CMOS device and AI hardware roadmap. Nelson received his B.S. from the University of Massachusetts, Amherst (2002) and his Ph.D. from Cornell University (2007), both in chemical engineering, and his doctoral work centered on the characterization of novel photoresist materials. He is co-inventor on over 50 patents and co-author on over 100 publications.
Analysis of edge placement error (EPE) at the 5nm node and beyond
Robert Socha
Fellow, ASML Brion
Abstract
The resolution concept of k1 is introduced along with various methods to reduce the k1 through resolution enhancement techniques. The edge placement error (EPE) of a 5nm node SRAM is examined in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization, and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matching error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Since SEPE is difficult to reduce, more emphasis needs to be placed on reducing the overlay EPE in order to reduce the total EPE. The ways to reduce overlay EPE in manufacturing include mark optimization to minimize effect of odd Zernike aberrations, minimization of the effect of process mark deformation on the alignment measurement, and minimization of wafer deformation through scanner stage and projection optics correction.
CV
Dr. Robert Socha is an ASML Fellow. In 1999, he joined ASML and works with customers to help them use ASML lithography equipment more effectively. He began his career at ASML in imaging, and later switched to metrology for overlay, alignment, and scatterometry. Dr. Socha received his B.S. degree in electrical engineering from University of Michigan in 1991 graduating Summa Cum Laude, and his Ph.D. degree in electrical engineering from the University of California at Berkeley in 1997. In 2011, Dr. Socha was elected fellow of SPIE.
Contact module progress and challenges in advanced CMOS technologies
Nicolas Breil
Applied Materials, USA
Abstract
As CMOS technology dimensions continue to scale, the contact module resistance becomes a fundamental bottleneck for the device performance improvement. In this invited talk, we will focus on the key components of the contact module and identify their respective impact on the device performance. We will review the process technologies available for the engineering of the contact module, and more specifically of the silicide/semiconductor interface. We will describe several recent technical breakthroughs and offer some perspectives on future developments.
CV
Nicolas Breil received his M.S. degree in physics and engineering from the National Institute of Applied Sciences in Toulouse, France, and a Ph.D. degree in semiconductor physics from the University of Sciences and Technology of Lille, STMicroelectronics, and CEA-LETI, France. His doctoral work focused on the integration and characterization of band-edge silicides and dopant segregation techniques for the contact resistance engineering of advanced CMOS devices. In 2008, he joined IBM in Crolles and in 2012 moved to East Fishkill, NY. While at IBM, he made key contributions to the development of the NiPtSi silicide module for the 22SOI technology and led the transition to Ti-silicide in the 14SOI technology. In 2015, he joined Applied Materials in Santa Clara, where he is currently a Technology Director and leads a development effort focused on the improvement of the contact module for advanced CMOS and memory technologies. He holds more than 30 U.S. patents and has published over 80 peer-reviewed papers.
Intermetallic compounds for Interconnect metal beyond 3 nm node
Junichi Koike
Professor, Dept. of Materials Science, Tohoku University, Japan
Abstract
As the technology node advances beyond 3 nm, copper is expected to face various challenges related to property, reliability, and process issues. To mitigate the foreseen problems, alternative interconnect metals have been proposed. Among those, some intermetallic compounds have low resistivity and high reliability without requiring liner and barrier layers. In the presentation, I will review our recent results of the property and reliability of intermetallic compounds for BEOL application. Their possibility and challenges will be discussed by making comparison with Cu, Co, Ru and other materials reported to date. Special attention will be given to CuAl2 for its low resistivity, good reliability in electromigration and TDDB, as well as good gap filling. I will also introduce collaborative effort in developing 300 mm process for sputter target production, PVD gap filling and CMP processes.
CV
Junichi Koike is a professor in the Dept. of Materials Science at Tohoku University. He received BS and MS in metallurgy from Tokyo Institute of Technology, Japan and Ph. D. in Materials Science from Northwestern University in the USA in 1989. He worked for Argonne National Laboratory, Los Alamos National Laboratory, and Oregon State University, before he joined Tohoku University in 1994. His seminal work of the self-forming barrier with Cu-Mn metallization has been widely implemented in semiconductor industry. He gave a numerous number of invited presentations at major international conferences, including IEDM, VLSI, IITC, IRPS. He has authored more than 200 papers, and holds more than 50 patents worldwide. Major awards include The Commendation for Science and Technology by the Japanese Government (MEXT); Honda Frontier Award from Honda Memorial Foundation; Tanigawa-Harris Award, Masumoto Hakaru Award, Meritorious Award, Best Paper Award from The Japan Institute of Metals and Materials; and IITC Michael Lerme Best Paper Award.
Commercialization of MRAM – Historical and Future perspective
Sumio Ikegawa
Distinguished Member of the Technical Staff in Technology R&D Department, Everspin Technologies Inc., USA
Abstract
Magnetoresistive random access memory (MRAM) has evolved into a superior form of non-volatile working memory since its research started in the early 1990’s. Currently, MRAM has found commercial acceptance in standalone memory applications with up to 1 Gb capacity and in embedded memories where embedded NOR flash and SRAM face scaling difficulties. Existing demonstrations of the scaling properties for pMTJ-based STT-MRAM show the promise of this technology to compete with existing memories and expand its potential application space because of its non-volatility, high speed, robust endurance, and system power savings capability. In this paper, we first review the history of successful commercialization of MRAM. Based on that, we provide a future perspective of MRAM products.
CV
Sumio Ikegawa has over 18 years of experience in research and development (R&D) of magnetoresistive random access memory (MRAM), focusing on device modeling, device design, and development of reliability. He joined Everspin Technologies Inc., Chandler, AZ, USA, in 2014 as a Distinguished Member of the Technical Staff in Technology R&D Department, where he is currently responsible for planning and developing advanced technologies for future MRAM products. Before joining Everspin, he had worked for Toshiba corporation, Japan, for 31 years, where he started his research and development of MRAM. He received the B.S. degree in applied physics from the University of Tokyo, Japan, in 1981, the M.S. degree in physics from Tohoku University, Japan, in 1983, and the Ph.D. degree in applied physics from the University of Tokyo, Japan, in 1993. He has authored or co-authored more than 100 papers published in journals and conference proceedings and holds over 30 active U.S. patents. He is a member of IEEE, APS, and the Magnetic Society of Japan. He is serving on the scientific committee of International Memory Workshop (IMW).
Enabling Ferroelectric Memories in BEOL – towards advanced neuromorphic computing architectures
David Lehninger
Project manager, Fraunhofer Center for Nanoelectronic Materials, Fraunhofer, Germany
Abstract
Advanced non-volatile memory concepts like FE random‐access memories (FeRAMs) and FE field‐effect transistors (FeFETs) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) to the drain or gate contact of a front‐end‐of‐line (FEoL) transistor, respectively. Both concepts can be used to increase the effective memory area of the chip without introducing major changes in the FEoL technology. In addition, the (BEoL) FeFETs is of great interest for advanced neuromorphic computing architectures. Zirconium doped HfO2 crystalizes in the FE phase at comparatively low temperatures and is thus promising for the BEoL integration. This talk will introduce the above-mentioned memory concepts and describe important steps to optimize zirconia doped HfO2 films to meet the requirements for the BEoL integration.
CV
David Lehninger is working as project manager at the Fraunhofer Center for Nanoelectronic Materials, which belongs to the Fraunhofer Institute of Photonic Microsystems (IPMS). His main scientific interest is the integration of ferroelectric materials into the back end of line of modern integrated circuits as well as the structural and electrical characterization of test structures and devices in the field of emerging non-volatile memories. Before he joined Fraunhofer in 2018, he successfully finished his Ph.D in nanoscience at the TU Bergakademie Freiberg.
EM performance improvements for Cu interconnects with Ru-based liner and Co cap in advanced nodes
Koichi Motoyama
BEOL Metal Integration, IBM Research
Abstract
It has been observed that void-free Cu fill, interface control for both Cu/liner (trench sidewall and bottom) and Cu/cap (trench top), and grain size engineering are critical to improve Electromigration (EM) performance for Cu interconnects in the case of using Ru liner and Co cap. Especially, Co diffusion from the cap into a Ru liner (resulting in Co depletion at the top of Cu lines) is one of the root causes of EM degradation. A novel Co-doped Ru liner has been developed, which demonstrates a significant EM performance boost by addressing the Co diffusion issue. This Co-doped Ru liner is shown to be a promising liner of choice for Cu interconnects in advanced nodes.
CV
Koichi Motoyama received M.S. degree in Chemistry from Keio University, Yokohama, Japan in 1998 and received Ph.D. degree in Materials Sciences from Tohoku University, Sendai, Japan in 2014, respectively. He has been a Senior Engineer for BEOL integration at IBM Research since 2013. Prior to joining IBM, he was employed at Renesas Electronics from 1998 until 2012 as a principal engineer and manager responsible for BEOL metallization. Dr. Motoyama has published or presented over 40 papers and has multiple issued international patents.
On-die interconnect technologies for future technology nodes
Mauro Kobrinsky
Intel
Abstract
Rapidly evolving requirements for on-die interconnects resulting from scaling and performance needs of current and future products is bringing about an exciting acceleration of the rate of innovations. In this paper, we will link evolutionary technology node needs and disruptive trends to interconnect requirements and to the key technologies needed to address future challenges, which include the introduction of new materials, as well as new geometries and structures.
CV
Mauro J. Kobrinsky received his Ph.D. from the Massachusetts Institute of Technology in 2001. He has been with Intel’s Components Research for 19 years; his current position is Director of Interconnects Structures and Architectures. He has contributed to all areas of interconnects research, including process integration, metallization, dielectrics, reliability, interconnects modelling, clock distribution, I/O, photonics, functional materials, 3D integration, and Die-Package interactions. He holds over 35 patents, and has more than 35 papers and conference presentations. Dr. Kobrinsky has served as a member of the Technical Advisory Board for the Interconnects and Packaging Science area of the Global Research Consortium (GRC), and as a member of the ITRS Interconnect roadmap team.
Reliability Characterization on Advanced FinFET Technology
Kihyun Choi
Samsung Electronics, South Korea
Abstract
In this paper, we will report the reliability characterization of advanced FinFET technology in terms of FEOL, MOL, and BEOL reliability. We found that the use of EUV single patterning of MOL and BEOL could improve reliability compared to ArF multiple patterning technology. Also we will review the reliability model of the MOL and BEOL TDDB.
CV
Kihyun Choi received Ph.D degree in electrical engineering from The University of Tokyo, Japan under Prof. Yasuhiko Arakawa in 2013. From 2013 to 2015, he worked on developing highly efficient quantum devices using semiconductor nanostructures at NanoQuine (Institute for Nano Quantum Information Electronic) of The University of Tokyo. From late 2015, he joined Samsumg Foundry Business, Korea. He is working on reliability characterization of Samsung’s advanced process technology.
Technological Influences in Designing and Building a Wafer Scale Interconnect
Gary Lauterback
CTO and Co-Founder, Cerebras Systems
Abstract
VLSI chips have grown from less than 10 mm^2 50 years ago to more than 800 mm^2 today. There are distinct advantages to keeping all of a compute systems processing on silicon: lower power, lower latency, and higher bandwidth as well as lower cost are some of the benefits. In the past there have been commercial attempts to break the single-reticle barrier while not transitioning off of a monolithic silicon substrate. To date, only Cerebras Systems has succeeded in shipping products that break the reticle barrier. The Cerebras wafer scale interconnect spans more than 49,000 mm^2 of monolithic silicon. In this talk we will discuss the influences of the silicon technology on the architecture and implementation of the wafer scale interconnect used in the Cerebras CS-1 system. The influences of silicon yield, power dissipation and delivery, cooling, cost and performance will all be covered. It was only through a deliberative process of design-technology co-optimization that it was possible to build a wafer scale system.
CV
Gary’s career in the computer industry spans more than 40 years and includes working at Bell Laboratories, Data General, ROLM, Sun Microsystems, LSI Logic, AMD, SeaMicro and Cerebras Systems. At Sun Microsystems Gary was the chief architect of the UltraSPARC-III and UltraSPARC-IV microprocessors. At Sun Laboratories he was the chief architect of the DARPA HPCS Petascale computing project. Most recently he has been CTO and co-founder at both SeaMicro and Cerebras Systems where he has led their innovative technologies at both the system and silicon levels. SeaMicro was a pioneer in the microserver category and Cerebras Systems has built the world’s first and only wafer scale silicon system. Gary currently holds more than 50 patents.
Resistive memories for neuromorphic hardware
Elisa Vianello
Senior scientist, CEA-Leti, France
Abstract
Resistive memory technologies, also known as memristive devices, have been widely studied for in-memory computing architectures and neuromorphic electronic circuits. Compared to conventional systems, these solutions offer promising advantages in terms of energy efficiency and computing power when processing AI workloads. However, these chips are still only at an early stage of development and thus it is important to explore the challenges and opportunities for the field. From the hardware standpoint, more and more on-chip memory is required to address the ever-increasing requirements of AI applications. On the system and circuit design side, one of the main challenges is obtaining accurate results with not ideal, noisy computing components. Here, we present new paths to achieve high-density 3D resistive memories and the associated challenges. Second, we report an approach that exploits conductance variability of resistive memory technologies in its favor to achieve low-power accurate AI processing.
CV
Elisa Vianello is a senior scientist at CEA-Leti. She joined the institute in 2011 after spending one year on the research staff at Fondazione Bruno Kessler, Trento. Her current research interests concern the development of new technologies for bio-inspired neuromorphic computing, with special focus on resistive switching memory devices (RRAM) and phase change memory (PCM). She has authored or co-authored 4 book chapters and more than 100 technical papers. She is coordinator of the “”MeM-Scales”” (2020-2022) European project (H2020) focused on the co-development of a novel class of algorithms, devices and circuits that reproduce multi-timescale processing of biological neural systems.
She also is associate editor of the APL special issue on Emerging Materials in Neuromorphic Computing (February 2020) and of the IEEE Transactions on Circuits and Systems –II (2020-2021). She received the PhD in Electrical Engineering from the Università degli Studi di Udine (Italy) and the Grenoble Institute of Technology (INPG, France) in 2010.
She also is associate editor of the APL special issue on Emerging Materials in Neuromorphic Computing (February 2020) and of the IEEE Transactions on Circuits and Systems –II (2020-2021). She received the PhD in Electrical Engineering from the Università degli Studi di Udine (Italy) and the Grenoble Institute of Technology (INPG, France) in 2010.